The invention relates to the field of computers which have to process intensive loads. This may involve computer systems dedicated to graphical applications or numerical calculation applications, but it may also involve processors included in signal or data processing chains. Intensive computing machines may be of different types. In most cases, they comprise a plurality of processors among which the parts of an application will be distributed, while the processors share common memory areas. In SMP (Shared Memory MultiProcessor) architectures, the processing operations are distributed among at least two processors which share access to the same common memory. In Distributed Memory Multiprocessor architectures, the distribution of the processing operations will depend on the relative locations of the different processors and stored data, i.e. on the physical architecture and not only on the application. A different form of parallelism may result from processor command instruction sets. This occurs, for example, in the case of SIMD (Single Instruction, Multiple Data) processing operations, in support of which specific instruction sets have been added to the normal instructions. Different instruction sets are thus known, notably SSE (Streaming SIMD Extensions) or AltiVec (trademark registered by Apple, IBM and Freescale Semiconducteurs to designate an SIMD instruction set operating on 128-bit vectors). Acceleration techniques also exist which are based on the realization that a single processor may be perfectly adapted to some of the processing operations that a computer has to perform, whereas, for certain applications, it may require assistance in the form of an additional processor installed on an add-on accelerator card. In this case, the traditional architecture most often involves all of the specialized applications being executed on the add-on card processor. The host structure processor is then underutilized since it will only manage the input/output from the additional processor. For given performance levels, this may result in the need to overdimension the add-on card processor, which will inevitably incur additional cost. The architecture is therefore not optimal.